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Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs | IEEE Journals & Magazine | IEEE Xplore

Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs


Abstract:

This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solv...Show More

Abstract:

This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solved optimally only by tackling its subproblems jointly, the exceeding complexity of such a task leads to a decomposition into two phases. The partitioning phase is based on a new graph-theoretic approach, which aims to obtain near optimality even if performed independently from the subsequent phase. For the scheduling phase, a new integer linear programming formulation and a heuristic approach are developed. Both take into account configuration prefetching and module reuse. The experimental results show that the proposed method compares favorably with existing solutions.
Page(s): 662 - 675
Date of Publication: 21 April 2009

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