Systematic defects within integrated circuits (ICs) are a significant source of failures in nanoscale technologies. Identification of systematic defects is therefore very important for yield improvement. This paper discusses a diagnosis-driven systematic defect identification methodology that we call layout analysis for systematic IC-defect identification using clustering (LASIC). By clustering images of the layout locations that correspond to diagnosed sites for a statistically large number of IC failures, LASIC uncovers the common layout features. To reduce computation time, only the dominant coefficients of a discrete cosine transform analysis of the layout images are used for clustering. LASIC is applied to an industrial chip and it is found to be effective. In addition, detailed simulations reveal that LASIC is both accurate and effective.