Abstract:
Multicore instruction-set simulation (MCISS) has become more and more important due to tremendous increase in number of multicore designs. To boost the speed of MCISS, on...Show MoreMetadata
Abstract:
Multicore instruction-set simulation (MCISS) has become more and more important due to tremendous increase in number of multicore designs. To boost the speed of MCISS, one of the most effective and commonly used approaches is parallel simulation. However, timing synchronization must be applied to ensure accurate simulation results of parallel MCISS, and may induce huge synchronization overhead. In this paper, we propose a highly efficient and effective parallel MCISS approach by synchronizing timing before each synchronization function (SF) call. We improve the applicability of the state-of-the-art critical-section-level simulation approach with a generic blocking/nonblocking send/receive model covering all types of SFs. To further reduce synchronization overhead, we also introduce optimization methods such as a hybrid scheduling technique and provide an analysis algorithm that helps the designers to choose the host platform with the best simulation performance. Experiments show that the proposed approach attains a simulation speed of up to 285 MIPS, while producing accurate timing and functional results.
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 34, Issue: 11, November 2015)