Efficient analysis of on-chip power delivery networks is one of the most challenging problems facing the electronic design automation industry today. The fast dc and transient simulation of power grids is necessary to determine the proper operation of the integrated circuits at the design phase, but is made very difficult by the sheer size of modern power grids, reaching quite a few million nodes in nanometer-scale integrated circuits. This paper presents two efficient and highly parallel preconditioning mechanisms for the analysis of large-scale power grids of near-2-D structure (with small via resistances) or 3-D structure (with large via resistances) by iterative solution methods. The proposed preconditioners approximate the matrices of practical power grids well enough to ensure fast convergence of the iterative method, while their application within the core of the method is based on a fast transform solver which makes use of a series of independent fast Fourier transforms. Apart from the near-optimal operation complexity, the main characteristics of a fast transform solver are the large degree of multilevel parallelism and low memory requirements, which enable harnessing the computational resources of massively parallel architectures like graphics processing units (GPUs). Experimental evaluation of the proposed methodology on a set of large-scale industrial benchmarks demonstrates nearly two orders of magnitude speedup and reduction in memory footprint over parallel implementations of state-of-the-art direct and iterative methods, when GPUs are utilized.