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Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation | IEEE Journals & Magazine | IEEE Xplore

Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation


Abstract:

High-cost specification tests of analog/RF devices have become a bottle-neck in reducing the overall cost of high-volume manufacturing (HVM) of systems on chip (SoCs) due...Show More

Abstract:

High-cost specification tests of analog/RF devices have become a bottle-neck in reducing the overall cost of high-volume manufacturing (HVM) of systems on chip (SoCs) due to lengthy testing time and expensive test equipment. Especially for fabless semiconductor companies, test time reduction (TTR) is becoming an important priority for developing cost-effective design and manufacturing flow of SoCs. Toward this end, numerous approaches have been developed. In this paper, we point out an important practical issue in implementing feature-selection-based low-cost analog/RF test scheme: in HVM, similar specification tests are often bundled as test suites, which are tested as a whole function by automatic test equipment. Removing some tests in one test suite does not provide much saving on device testing time. We then propose a test-suite-based analog/RF TTR approach using canonical correlation, which aims at identifying correlations between two multivariate sets. We further enhance the incurred test escape by applying a data-driven defect-oriented approach. Experimental results in high-volume industrial data confirm the superiority of the proposed approach over existing methods in terms of both TTR and defective parts per million level.
Page(s): 2143 - 2147
Date of Publication: 29 March 2016

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