In deep-submicron very large scale integration manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such as coupling capacitance. Traditional tile-based method for fill insertion usually results in very large number of fills, which increases the cost of layout storage. In advanced technology nodes, solving the tile-based dummy fill design is more and more expensive. In this paper, we propose a high performance dummy fill insertion framework based on geometric properties to optimize multiple objectives simultaneously, including coupling capacitance, density variations and gradient. The experimental results for ICCAD 2014 contest benchmarks demonstrate the effectiveness of our methods.