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Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures | IEEE Journals & Magazine | IEEE Xplore

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures


Abstract:

Quantum computing has raised great interests for its potential to achieve an asymptotic speedup on specific problems. Current quantum devices suffer from noise which need...Show More

Abstract:

Quantum computing has raised great interests for its potential to achieve an asymptotic speedup on specific problems. Current quantum devices suffer from noise which needs robust and scalable error-correcting schemes. Topological quantum error correction (TQEC) is among the most promising error-correcting techniques with exponential suppression of error with linear increase of space-time complexity. In this paper, we present the first work to explore space-time optimization between 1-D and 2-D architectures for TQEC circuits. We prove the NP-hardness of the qubit routing problem in the layout synthesis and propose an efficient algorithm to optimize space-time volumes for both 1-D and 2-D qubit architectures with promising experimental results.
Page(s): 1574 - 1587
Date of Publication: 06 October 2017

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