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On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries | IEEE Journals & Magazine | IEEE Xplore
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On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries


Abstract:

One approach for achieving a robust integrated system centers on first performing test during runtime, then identifying the locations of any faults (or potential faults),...Show More

Abstract:

One approach for achieving a robust integrated system centers on first performing test during runtime, then identifying the locations of any faults (or potential faults), and finally repairing/replacing/avoiding the affected portion(s) of the system. Conventional fault dictionary approaches can be used to locate failures but are limited to simplistic fail behaviors due to the significant computational resources required for dictionary generation and memory storage. Several contributions are described to overcome these limitations, and include: 1) enhancement of an unspecified-transition fault model (called here the transition-X fault model, or TRAX) for capturing the misbehaviors expected from scaled technologies; 2) development of a hierarchical dictionary that only localizes to the level required; and 3) the design of a scalable architecture for retrieving and using the hierarchical dictionary for on-chip failure diagnosis. The OpenSPARC T2 processor and other circuits are used in experiments to demonstrate the low-overhead, accurate diagnosis of early life and wear-out failures, using TRAX dictionaries that are over five orders of magnitude smaller than full-response dictionaries.
Page(s): 322 - 334
Date of Publication: 07 February 2018

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