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A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits | IEEE Journals & Magazine | IEEE Xplore
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A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits


Abstract:

Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a ...Show More

Abstract:

Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of interlayer via density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs. The proposed technique provides test schedules with minimum test time under power consumption and probe pad constraints.
Page(s): 1942 - 1955
Date of Publication: 08 August 2018

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