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Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II | IEEE Journals & Magazine | IEEE Xplore

Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II


Abstract:

This article gives a detailed insight on a machine learning procedure to infer quasistatic quantities of electrostatic discharge (ESD) protection structures from their in...Show More

Abstract:

This article gives a detailed insight on a machine learning procedure to infer quasistatic quantities of electrostatic discharge (ESD) protection structures from their instance parameters in a netlist. It resorts to a dataset of transmission line pulse (TLP) I-V curves that have been obtained from numerous transient electrical simulations. The tuning of machine learning algorithms and the quantification of their generalized prediction performances on out-of-sample data are performed by means of nested cross-validation. Resulting fitted analytical models are encompassed in a tool called ESD IP Explorer in charge of providing a systematic and scalable ESD verification methodology. This tool, which has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures, is described in a former article.
Page(s): 3107 - 3117
Date of Publication: 24 December 2019

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