High speed data converter architectures such as pipelined analog-to-digital-converters (ADCs) typically consist of large capacitor arrays that are highly susceptible to systematic errors. Although significant efforts have been made in the literature to compensate linear and parabolic errors, the rotated parabolic components are less explored. These rotated parabolic components are responsible for spurious harmonics at the output of the converter, thereby degrading the linearity. In this article, we have investigated the origin of these rotated components, their impact on conversion linearity and discussed strategies to mitigate them. A placement technique along with one track routing solution, is proposed for complete compensation of the systematic errors. An algorithm is also provided to extend this technique to higher resolutions. The proposed technique is verified on the model of pipelined ADC, as well as current steering DAC. The incorporation of such technique results in near ideal linearity performance.