Layout migration is a fast methodology to generate the required layout for given circuits with different device attributes or different technology. By keeping the original layout topology, the previous design experience can help to keep the circuit performance. However, routing preservation is often not mentioned in previous layout migration techniques, which requires a complete rerouting to break the original style. Pan et al. (2015) proposed a topological slicing tree and a constrained delaunay triangulation (CDT) model to keep the routing style during migration. However, this approach may incur some missing nets after migration, which still requires tedious manual works to fix those nets. In this article, we propose a sequence pair (SP)-based placement migration methodology and a novel Cartesian detection line (CDL) model to preserve the routing styles in original layouts. By using the proposed approach, the routability information and routing behaviors can be preserved during layout migration. In order to prevent from missing nets, several refinement techniques are also proposed to fix unreasonable routing nets due to block displacement. In the experiments, the missing nets after migration can be reduced to almost zero with the proposed CDL model, which greatly reduces the extra design efforts.