With ever-increasing transistor density in nanoscale-integrated circuits, the impact of process variations on circuit performance and chip yield becomes dominant. To prevent failures in the field, simulation-based circuit optimization tools are performed during design time as a countermeasure. However, the efficiency of these tools requires accurate modeling of failure probabilities. Especially, for high-sigma problems such as yield estimation of memory cells, which require very high production yield, the failure rate assessment must be highly accurate. Importance sampling (IS) methods are deployed in this context to uncover very rare failure events, which cannot be revealed by standard Monte Carlo methods. Besides a highly accurate yield prediction model, the limited time budget of the simulation-based analysis tools has to be taken into account. Especially in conjunction with yield optimization techniques, the required number of circuit simulations for the failure rate estimation has to be substantially reduced. In this article, we propose a yield optimization method, which is based on a Bayesian optimization (BO) failure rate estimation technique for high-sigma yield extraction. The BO-based IS method is combined with a kernel density estimator for finding the most probable failure events, which have significant contribution to the chip yield. By integration into a global optimization framework, we show how the proposed yield optimization method can be applied to high-sigma yield optimization problems, such as memory cells. The experimental results indicate that the proposed method consumes only 5% circuit simulations to achieve the same optimization effect as the state-of-the-art yield optimizer techniques.