Timing errors of microelectronic circuits occur when the circuit timing specification is violated, i.e., the dynamic delay of circuits exceeds the circuit clock period. With the continuous scaling of CMOS technology, microelectronic circuits are increasingly susceptible to microelectronic variations such as variations in operating conditions. Such variations can cause delay uncertainty in microelectronic circuits, leading to timing errors. Circuit designers typically combat these errors using conservative guardbands in the circuit and architectural design, which can, however, cause significant loss of operational efficiency. In this article, we propose DEVoT, a supervised learning model that can predict the dynamic delay of functional units (FUs) under different operating conditions, clock speeds, and input workload. The main contribution of DEVoT is to jointly consider the impact of voltage, temperature, and input workload in path sensitization, hence predicting the dynamic delay. We measure the dynamic delay using switching activity generated through gate-level simulation of post place-and-route design in the TSMC 45-nm process. We characterize the delay of FUs under different operating conditions and input workload. We then extract useful features in the input workload that influences dynamic path sensitization. Using these features, we apply supervised learning methods to build DEVoT. Across 100 different operating conditions, four widely used FUs, and three datasets, DEVoT achieves, on average, less than 2% relative deviation from the ground truth and is $100\times$ faster than the gate-level simulation. We present two case studies using DEVoT. First, we use DEVoT to predict timing errors of FUs, and DEVoT achieves an average prediction accuracy at 98.04%. We further use DEVoT to estimate application output quality under different operating conditions, and DEVoT achieves an average estimation accuracy at 97% for two image processing applications. Second, we ...