The linearity of data converters fabricated in modern CMOS processes is typically limited by device mismatch. The dispersion in device placement primarily determines the extent of matching and hence, the chip yield. Till date, there exists no straightforward approach to precisely quantify dispersion over an array of identically laid out devices. The current research formulates new measures to quantify dispersion in device placement. The incorporation of such measures in traditional CAD optimization results in similar or even better correlation coefficients, but with a lighter computational footprint. This facilitates for faster optimization of large device placements without the need for high end processors.