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Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection | IEEE Journals & Magazine | IEEE Xplore

Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection


Abstract:

Hardware trojans (HTs) pose a critical security threat to modern integrated circuits (ICs) through malicious activities, including leaking critical information, executing...Show More

Abstract:

Hardware trojans (HTs) pose a critical security threat to modern integrated circuits (ICs) through malicious activities, including leaking critical information, executing unauthorized commands, and reducing IC lifetime. Traditional functional and structural verification approaches are inefficient in detecting stealthy Trojans effectively due to corner conditions and rare triggers. Furthermore, the existing approaches are limited to specific circuit designs and require formulating new models for other IC designs. In order to overcome such shortcomings, we introduce an IC topology and behavior-aware HT detection approach, where we extract different structural features of the underlying IC along with the behavioral information for HT detection. Structural features include node (gate) types and their respective counts and connectivity information extracted through an automated process using graph learning. These features are complemented with the behavioral information, such as operating frequency and bit-flip patterns under anomalous operating conditions (analogous to vaccination) and analyzed for Trojan detection. We propose a graph neural network (GNN) architecture where we utilize a graph convolution network (GCN) for detecting HTs. The proposed technique does not require the golden IC reference design for HT detection. Our model shows an average of around 93.15% accuracy while tested on an utterly unseen Trojan benchmark during the training phase. This shows that the proposed technique can learn the structural feature distribution of the ICs and their behavioral information to distinguish Trojan-free and Trojan-inserted circuits irrespective of the IC topology used in the training phase.
Page(s): 2852 - 2862
Date of Publication: 06 January 2023

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