The three major tasks in standard cell layout synthesis are transistor folding, transistor placement, and in-cell routing, which are tightly interrelated, but generally performed one at a time to reduce the extremely high complexity of design space. In this article, we propose an integrated approach to the two problems of transistor folding and placement. Precisely, we propose an optimal algorithm of search tree-based design space exploration, devising a set of effective speeding up techniques as well as dynamic programming-based fast cost computation. Our algorithm also incorporates the minimum oxide diffusion (OD) jog constraint, which closely relies on both of transistor folding and placement. To our knowledge, this is the first work that tries to simultaneously solve the two problems. In addition, to make an effective cell layout synthesis flow down to in-cell routing, we provided a fast in-cell routability estimation metric to be used in transistor placement and a method to explore cell layouts by varying the cell size constraint. Through experiments with the transistor netlists and design rules in the ASAP 7-nm library, it is shown that our proposed method is able to synthesize fully routable cell layouts of minimal size within very fast time for each netlist, outperforming the cell layout quality in the ASAP 7-nm library, which otherwise, may take several hours or days to manually complete layouts of the quality level comparable to ours.