In this article, we propose a comprehensive physical design flow specifically tailored for Monolithic 3-D (M3D) integration, a transformative technology for high-density and high-performance integrated circuit (IC) design in the post-Moore era. Unlike conventional RTL-to-GDS flows that heavily focus on utilizing commercial 2-D design tools, our design flow delves deep into the suboptimal issues inherent in implementing cross-tier connections, which are not adequately addressed by 2-D tools. Our proposed flow provides seamless optimization for such connections through three key design stages following pseudo-3D placement: 1) 3-D routing-aware tier partitioning that induces subtle imbalances in cell area distribution between tiers to maximize the utilization of monolithic intertier vias (MIVs); 2) MIV-guided detailed placement that optimizes the placement by strategically utilizing reserved whitespace for enhanced 3-D connections; and 3) MIV-aware 3-D routing that takes full advantage of the fine-tuned placement result. Experiment results using open-source benchmark circuits in advanced 7-nm technology nodes show that our proposed M3D design flow achieves up to 9.92% wirelength reduction per 3-D net, resulting in 76.70% improvement in worst negative slack, and an equivalently improved 60.28% energy-delay-product over the state-of-the-art M3D design flow on average even with challenging design conditions. We provide valuable insights into various factors for efficient and high-quality M3D IC design with effective solutions.