Loading [a11y]/accessibility-menu.js
Design and performance analysis of a low complexity digital clock recovery algorithm for software-defined radio applications | IEEE Journals & Magazine | IEEE Xplore
Scheduled Maintenance: On Monday, 27 January, the IEEE Xplore Author Profile management portal will undergo scheduled maintenance from 9:00-11:00 AM ET (1400-1600 UTC). During this time, access to the portal will be unavailable. We apologize for any inconvenience.

Design and performance analysis of a low complexity digital clock recovery algorithm for software-defined radio applications


Abstract:

In this paper, we propose and study a low-complexity digital clock recovery scheme suitable for implementation on programmable platforms, such as digital signal processin...Show More

Abstract:

In this paper, we propose and study a low-complexity digital clock recovery scheme suitable for implementation on programmable platforms, such as digital signal processing (DSP) or field-programmable gate-array (FPGA) platforms. Performance is established in terms of mean-square timing error and the required computational complexity, a key factor in the successful implementation of efficient software-defined radios (SDR). It is shown that the proposed algorithm achieves a superior performance when compared with the existing algorithms for a wide range of operating parameters. To assess complexity in terms of resource utilization, the FPGA platform is used to study the proposed algorithm along with other well-known algorithms.
Published in: IEEE Transactions on Consumer Electronics ( Volume: 56, Issue: 3, August 2010)
Page(s): 1258 - 1263
Date of Publication: 28 October 2010

ISSN Information:


References

References is not available for this document.