Random telegraph signal (RTS) noise has shown an increased impact on circuit performance at advanced complementary metal-oxide-semiconductor technologies. However, there is not yet a computer-aided design tool available to analyze such noise based on the statistical distribution of traps. In this paper, a new methodology is proposed to enable integrated circuit designers to analyze their circuits in the presence of RTS noise, thus providing an opportunity to mitigate the noise effect by design. Using a 3-D atomistic simulator, compact models that could accurately describe the device structure, doping profile, and statistically representative distribution of traps were extracted for SPICE simulation. Carrier trapping/detrapping was represented by a pair of compact models at different threshold voltages, hence defining the amplitude of RTS noise. The timing parameters of RTS noise were predicted based on the Shockley-Read-Hall statistics. Simulation results reveals that, while RTS noise from a single device may have little impact (¿I _out ¿ 0.0842 ¿A) on our test circuit performance, the cumulative effect from all devices (n = 30) in this relatively small circuit can be significant (¿I _out ¿ 0.5766 ¿A) . This reinforces the need for an RTS noise analyzer for deep-submicrometer circuit designs.