In this paper, a simple approach to reduce delay variations in domino logic gates is proposed. Previous analysis by the same authors showed that delay variations in domino logic are mainly due to the feedback loop implemented by the keeper transistor and the output inverter gate. Accordingly, the proposed strategy aims at reducing the loop gain associated with this feedback loop, and hence its impact on delay variations. In particular, a simple modified keeper is proposed to reduce the loop gain while keeping the same silicon area, noise margin, and nominal performance. The resulting delay variations associated with keeper insertion are shown to be lowered by approximately 50%. The proposed approach is assessed by means of simulations in 65-nm and 90-nm commercial CMOS technologies.