This paper presents the design and the VLSI implementation of an asynchronous cellular logic array for fast binary image processing. The proposed processor array employs trigger-wave propagation and collision detection mechanisms for binary image skeletonization, and Voronoi tessellation. Low power, low area, and high processing speed are achieved using full custom dynamic logic design. The prototype array consisting of 64 × 96 cells is fabricated in a standard 90 nm CMOS technology. The experimental results confirm the fast operation of the array, capable of extracting up to 2.78×10⁶ skeletons per second, consuming less than 1 nJ/skeleton. The asynchronous operation enables circular wave contours, which improves the quality of the extracted skeletons. The proposed asynchronous processing module consists of 24 MOS transistors and occupies 5.5 μm×7.4 μm area. Such array can be used as a co-processing unit aiding global binary image processing in standard pixel-parallel SIMD architectures in vision chips.