This paper proposes a reconfigurable decimator architecture for a multi-standard receiver front-end. This architecture is based on direct radio-frequency bandpass sampling and analog discrete-time multirate signal processing. The overall front-end consists of a low-noise amplifier followed by a tunable charge-domain sampler, a reconfigurable decimator, and an analog-to-digital converter. The proposed decimator is constructed as a cascade of four switched-capacitor filtering stages. The frequency responses and the decimation factors of these stages are digitally controllable thus enabling high reconfigurability. The advantages of the proposed design are a high image rejection, a low overall implementation complexity, and high flexibility. The feasibility of the design is evaluated by computer simulations.