A digital fractional- N phase-locked loop (PLL) frequency synthesizer based on a second-order ΔΣ frequency-to-digital converter (FDC) without conventional analog components was recently proposed and demonstrated experimentally to have performance in line with state-of-the-art analog PLLs. However, unlike analog PLLs or prior PLLs based on second-order ΔΣ FDCs, it is highly digital and does not require an analog charge pump or ADC, so it is well-suited to implementation in highly-scaled CMOS technology. This paper derives a linearized model of the new architecture and key equations which are necessary for the design of PLLs based on the architecture.