A high-order cascaded phase-locked loop (PLL) architecture using a sub-sampling delay-locked loop (DLL) is proposed to break the tradeoff between the loop bandwidth and the number of integrator in the feedback loop without significantly degrading the settling time or reference spur. A clock-skew-sampling phase detector is also proposed to extend the stable detection range of the sub-sampling phase detector. Implemented in a 65-nm CMOS process, a prototype of the proposed two-stage third-order cascaded PLL measures a 4.2-μs settling time, 1.05-ps integrated jitter, and -113-dBc/Hz in-band phase noise at a 2.1-GHz output frequency while consuming 3.84 mW at 1.2-V supply voltage and occupying a core chip area of 0.043 mm².