This paper proposes a new 10-transistor (10T) bitcell for robust operations at subthreshold voltages without any boost circuitry. Features of the proposed bitcell include: 1) differential pre-discharged bit-lines and a pair of decoupled access ports to resist disturbance; 2) footed latch for write assist; 3) spare latch-foot to fight against half-select disturbances; and 4) highly stacked pull-down structure to reduce both leakage and power. A bit-interleaved SRAM macro, constructed with the proposed 10T bitcell, is fabricated in 28 nm CMOS. The power consumption has been measured as 90 nW for 30 kHz access at 0.25 V, and 41 nW for retention at 0.20 V, of which the leakage is 31% better than the state-of-the-art design.