Fractional-N frequency synthesizers contain a divider controller which implements the fractional division. The interaction between the quantization noise from the divider controller and nonlinearities within the synthesizer will cause undesirable degradation of the output phase noise performance. The most common divider controller architecture is the Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM). Because the MASH DDSM suffers from performance degradation in the presence of nonlinearities, Galton et al. introduced a new divider controller architecture called the Successive reQuantizer (SQ). The SQ is designed to eliminate spurious tones caused by polynomial nonlinearities of a given order. A drawback of the SQ is that its hardware consumption is significantly higher than that of a MASH DDSM. A nested MASH-SQ hybrid has been introduced to achieve similar spectral performance to the SQ but with reduced hardware cost. In this paper, we present a design method for a nested MASH-SQ hybrid divider controller for fractional-N frequency synthesizers.