In this paper, the analysis of a current feedback compensation architecture compatible with pixels having the 2-transistors and 1-capacitor structure is evaluated. The aim of the circuit presented and analyzed, is to cleanly reach a programming pixel current level below 50 nA with an average 10% of error. Here, we also present the method to achieve robustness in the operation of the loop, observed through a series of measurements. All the peripheral blocks implementing the design are presented and analyzed through simulations as well as verified experimentally. Sources of noise are identified and eliminated, while the new techniques for better isolation from digital noise are described and tested on a newly fabricated driver. Multiple versions of the previously proposed circuit are outlined, simulated, fabricated, and measured to evaluate their performance.