In this paper, we present 3-D-DATE, a circuit-level dynamic random access memory (DRAM) area, timing, and energy model that models both the front and back end of 3-D integrated DRAM designs from 90–16 nm, across a broader range of emerging transistor devices and through-silicon vias. This paper improves upon previous studies by providing detailed process models all the way down to the 16-nm technology node and incorporating DRAMs implemented with emerging gate transistor devices. Finally, we validate the model against both several commodity planar and 3-D DRAMs, from 80- to 30-nm process nodes, with the following metrics: energy with a mean error of 5%–1% and a standard deviation up to 9.8%, speed with a mean error of 13%–27%, and a standard deviation up to 24% and area within 3%–1% and a standard a standard deviation up to 4.2%.