This paper proposes a new design methodology to explore the state-of-the-art approximate adders for accelerator architectures conceived in the realm of multiplier-less multiple constant multiplication optimization problem. The proposed methodology is composed of: 1) a search heuristic to seek faster and feasible approximate configurations for the architectures under evaluation; 2) low-power techniques regarding hybrid approximate adders design for accelerators based on trees of shift-and-add operations; 3) high-performance evaluation by exploring parallel prefix adders and low power analysis through the use of the adder optimized by a commercial synthesis tool in the precise part of the approximate adders; and 4) energy efficiency analysis by considering both the approximate techniques and voltage over scaling estimation. Furthermore, improvements are proposed for the state-of-the-art approximate adders under evaluation in this paper. Two case studies are considered to assess the proposed methodology: 1) Gaussian image filter and 2) Sobel operator. The precise and approximate image filters were described in very high-speed integrated circuits hardware description language regarding the proposed methodology. Results are shown after synthesis to a 45-nm standard cell-based technology, where energy reductions ranging from 7.7% up to 73.2% were experienced for multiple levels of quality considering the applications under analysis.