A systematic approach is presented to analyze the switching pair linearity of low intermediate frequency (IF) up-conversion mixers. The approach explicitly divides the switching pair operation of the mixer into two steps-conversion of the low IF input to the common-source node voltage, in a common-mode domain, and conversion of the common-source node voltage to the output, in a differential-mode domain. In this way, closed-form formulas of the signal gain and third-order intermodulation distortions (IMD3) are derived, demonstrating that the even harmonics (mainly twice local oscillator frequency harmonics) on the common-source node affects the linearity performance significantly. As a result, the mixer linearity is strongly sensitive to the common-source node parasitic reactance. To suppress the even harmonics, we adopt a harmonic-trapping (HT) capacitor and demonstrate 9.1 dB improvement in OIP3 from the fabricated chip prototypes. The analysis approach and HT technique are further validated by well-matched analytical predictions, simulation and measurement results.