A non-linear analytical method is presented for global placement of logic cells in an IC, based on algorithms inspired in Dynamic Systems Theory, also known as Chaotic Systems. The related developed tool is called Chaotic Place. The two-dimensional structure of the cells of a circuit was obtained by the reconstruction of a Strange Attractor (Takens' Theorem). The experiment was tested in the field programmable gate arrays (FPGAs) using the “FPGA Place-and-Route Challenge” benchmarks. For comparison of results, the Half-Perimeter-Wire-Length (HPWL) was used as the main metric. The experiment results show a 6% reduction in wirelength, on average, when compared to the state-of-the-art placement tools for homogeneous FPGAs.