A digitally controlled oscillator (DCO) is presented that utilizes the non-linearity of a resistor-triode combination in conjunction with a weak latch to mitigate the supply sensitivity of inverter-based delay cells and remain supply noise insensitive over a wide range of supply variation. A proofof-concept prototype for the DCO in 65 nm-CMOS process occupies 90×210 μm² area and consumes 2.25 mW operating over a range of 0.9-1.4 GHz output frequency. At 850 Mv-supply voltage, the frequency pushing of DCO is zero at the optimal point and remains less than 10% over a large excursion of 50 mV_pp. When embedded into an all-digital phase locked loop, closed-loop measurements demonstrate that supply noise with 50 mV_ppmagnitude does not impact the loop dynamics.