This paper presents the first low-complexity realization of an LDPC-code sparse code multiple access (SCMA) receiver with a high-throughput LDPC decoder and a multi-mode SCMA detector. The minimum mean-square error with parallel interference cancellation (MMSE-PIC) algorithm is adopted in the SCMA detection. The modified user-node operations in the MMSE-PIC-based message-passing detector improve the convergence rate in error performance. The proposed receiver also supports multi-user iterative detection and decoding (MU-IDD) to improve the error rate performance. The proposed receiver supports both 4×6 and 8×12 SCMA systems. The proposed MU LDPC decoder has a 57.1% lower hardware complexity than the direct-mapped design that is achieved through hardware sharing and memory access scheduling. Designed in a 40-nm CMOS technology, the SCMA receiver integrates 10.9M logic gates in an area of 3.382 × 3.382 mm². The proposed design achieves a gross throughput of 1.198 Gb/s and 599 Mb/s for 8 × 12 and 4 × 6 SCMA systems, respectively, under a practical situation. It dissipates 813 mW at a clock frequency of 300 MHz from a 0.9-V supply.