Phase coherent, frequency hopping direct digital synthesizer (DDS) and Type-II phase locked loop (PLL) circuits are presented in this paper. The proposed approach eliminates the memory effects of prior frequency states in the phase (DDS) and fractional (PLL) accumulators by employing a master accumulator with a fixed increment and multiplying its output to generate the appropriate phase and fractional outputs. This approach allows for an arbitrary sequence of frequency hops, since it is not based on multiple simultaneous accumulators to store phase. We present phase coherent topologies for standard and parallelized DDS circuits, a fractional-N PLL and a multistage sigma-delta modulator (MASH)-111 fractional-N PLL, along with mathematical analysis showing phase coherency. We also present measured results of parallelized DDS and MASH-111 fractional-N PLL hardware.