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A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line | IEEE Journals & Magazine | IEEE Xplore

A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line


Abstract:

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical...Show More

Abstract:

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where R2 maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps.
Page(s): 2685 - 2692
Date of Publication: 09 March 2020

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