Abstract:
In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical...Show MoreMetadata
Abstract:
In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where R2 maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 67, Issue: 8, August 2020)