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A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier | IEEE Journals & Magazine | IEEE Xplore

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier


Abstract:

This paper introduces a 12 bit 2.5 bit/cycle SAR-based pipeline ADC employing a self-bias gain boosting amplifier. The single-stage amplifier achieves a low-frequency gai...Show More

Abstract:

This paper introduces a 12 bit 2.5 bit/cycle SAR-based pipeline ADC employing a self-bias gain boosting amplifier. The single-stage amplifier achieves a low-frequency gain of 37 dB, while consuming 1.3 mW of power consumption with 1.3 V of analog power supply. A 2.5 bit/cycle SAR ADC realizes as the sub-ADC in each stage, and reduces both power consumption and silicon area. A two-channel sampling architecture is employed to double the sampling rate and thereby maximize circuit efficiency. A digital calibration technique is used to reduce non-linearity and mismatches due to the RDAC, as well as gain error and offset of the open-loop residue amplifier. The prototype ADC was fabricated in TSMC 40-nm technology, and consumes 10.71 mW with 1.1 V / 1.3 V digital / analog power supplies. When operating at 125 MS/s, the ADC achieves an SFDR of 66.59 dB before calibration and 80.3 dB after calibration when measured at Nyquist frequency. The experimental results show a Walden FoM of 101 fJ/c.-s. before calibration and 47 fJ/c.-s. after calibration.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 67, Issue: 11, November 2020)
Page(s): 3618 - 3629
Date of Publication: 13 July 2020

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