Integrating type analog-to-digital converters (ADC) used in column-parallel CMOS image sensors trade conversion speed with size, power, and complexity to achieve optimal performance. A new integrating ADC architecture called single-slope look-ahead ramp (SSLAR) ADC is introduced in this paper. It utilizes a statistical approach and code-prediction methods to improve the conversion speed of standard single-slope ramp (SSR) ADC. It is shown that SSLAR ADC reduces power consumption while achieving an increased frame rate. This is achieved by the SSLAR algorithm that was optimized for column-parallel CMOS active pixel sensor (APS) imager architecture. A 10-bit SSLAR ADC was designed in a 0.5μm CMOS (2P3M) process and integrated with a column-parallel CMOS image sensor that has 200 × 150 array with 15μm pixels. Measurements showed that a 6× frame rate increase can be achieved while reducing power consumption 13% with minimal impact on image quality.