This paper describes all-digital enhancements for digital fractional-N phase-locked loops (PLLs) based on delta-sigma (ΔΣ) frequency-to-digital converters (FDCs). The enhancements include an improved dual-mode ring oscillator (DMRO)-based ΔΣ FDC architecture and a digital background calibration technique that compensates for the ΔΣ FDC's forward path gain error. The improved ΔΣ FDC has significantly relaxed timing constraints and a 3× smaller phase-frequency detector output pulse-width span relative to the prior art, which make it simpler to implement and amenable to higher-frequency reference signals. The calibration technique compensates for non-ideal DMRO frequencies in the digital domain. It eliminates the need to tune the DMRO instantaneous frequencies as a function of the PLL output frequency, thereby simplifying the DMRO implementation, and it also improves the phase noise performance of PLLs with high loop bandwidths.