Processing math: 0%
Construction and Application of a Neuromorphic Circuit With Excitatory and Inhibitory Post-Synaptic Conduction Channels Implemented Using Dual-Gate Thin-Film Transistors | IEEE Journals & Magazine | IEEE Xplore
Scheduled Maintenance: On Monday, 27 January, the IEEE Xplore Author Profile management portal will undergo scheduled maintenance from 9:00-11:00 AM ET (1400-1600 UTC). During this time, access to the portal will be unavailable. We apologize for any inconvenience.

Construction and Application of a Neuromorphic Circuit With Excitatory and Inhibitory Post-Synaptic Conduction Channels Implemented Using Dual-Gate Thin-Film Transistors


Abstract:

Enabled by the availability of both excitatory and inhibitory post-synaptic currents, a biological neural network is inherently capable of implementing more sophisticated...Show More

Abstract:

Enabled by the availability of both excitatory and inhibitory post-synaptic currents, a biological neural network is inherently capable of implementing more sophisticated non-monotonic classification schemes. While such currents are readily emulated in a software-based artificial neural network using both positive and negative synaptic weighting factors, the same is not as straight forward in a hardware implementation. In this work, two dual-gate thin-film transistors with effectively infinite direct-current input impedance are deployed to construct the excitatory and inhibitory conduction channels of an artificial synapse. The utility of a hardware-based artificial neural network constructed using such synapses is demonstrated by its deployment in the implementation of the complete set of sixteen 2-input binary logic functions exhibiting both monotonic and non-monotonic behavior. The set of weighting factors needed for the implementation of each function are determined using a neuromorphic feed-forward training algorithm based on gradient-descent. While some of the functions can be implemented using the simplest reconfigurable \mathbf {2\times 1} network, all 16 of the functions can be implemented using a deeper, reconfigurable \mathbf {3\times 2\times 1} network.
Page(s): 1582 - 1589
Date of Publication: 10 January 2024

ISSN Information:

Funding Agency:


References

References is not available for this document.