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A Fast ULV Logic Synthesis Flow in Many-- CMOS Processes for Minimum Energy Under Timing Constraints | IEEE Journals & Magazine | IEEE Xplore

A Fast ULV Logic Synthesis Flow in Many-V_{t} CMOS Processes for Minimum Energy Under Timing Constraints

Publisher: IEEE

Abstract:

Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, t...View more

Abstract:

Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (V dd ) and threshold (V t ) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the V dd /V t MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all V dd /V t pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC'99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4× compared to a conventional flow with V dd scaling only.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: 59, Issue: 12, December 2012)
Page(s): 947 - 951
Date of Publication: 10 January 2013

ISSN Information:

Publisher: IEEE

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