This brief presents a majority-voting 1-tap speculative decision-feedback equalization (DFE) architecture wherein the current-mode-logic (CML) selector after the slicers is replaced with a CML majority voter with two instead of three transistors in the stack, thereby resulting in improved speed and increased voltage headroom (or lower supply voltage operation). Compared with the traditional CML selector, the majority voter shows around 50% delay reduction at the same bias conditions and 25% reduction in supply. A receiver with the proposed majority-voting DFE is implemented in 0.13- μm CMOS process. With the DFE enabled, the receiver is able to equalize a 20-in channel over an FR4 board with 22-dB Nyquist loss at 4.5 Gb/s. The whole receiver core occupies 0.14 mm² and consumes 12.4 mW.