A phase-rotator-based all-digital phase-locked loop for spread-spectrum clock generation is presented. It combines a dual-tone triangular and a random modulation profile to achieve a balance between electromagnetic interference reduction and broadband jitter generation. The test chip, fabricated using a 90-nm CMOS process, achieves a 43-dB total EMI reduction at the resolution bandwidth of 100 Hz without incurring a notable bit-error-rate penalty at the receiver's side and consuming only 15.8 mW at 6 GHz from a 1-V supply.