A 10-bit 40-MS/s time-domain two-step analog-to-digital converter (ADC) in a 0.18-μm CMOS process is presented. The proposed ADC is realized without any high-gain amplifiers and its calibration time requires only 622 clock cycles, which is over 10 times less than prior digitally calibrated ADCs. The measured spurious-free dynamic range (SFDR) and signal-to-noise-plus distortion ratio (SNDR) are 61.3 dB and 53.8 dB at 40 MS/s, respectively. The power and area are 6.1 mW and 0.75 mm², respectively.