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Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression | IEEE Journals & Magazine | IEEE Xplore

Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression


Abstract:

This brief proposes a new compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed scheme stores on...Show More

Abstract:

This brief proposes a new compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed scheme stores only the range of state metrics as well as two indexes of the maximum and minimum values, while the previous compression methods have to store all of the state metrics for initializing the following iteration. We also present a hardware-friendly recovery strategy, which can be implemented by simple multiplexing networks. Compared to the previous work, as a result, the proposed compression method reduces the required storage bits by 30% while providing the acceptable error-correcting performance in practice.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: 63, Issue: 2, February 2016)
Page(s): 211 - 215
Date of Publication: 28 September 2015

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