This brief presents a logarithmic analog-to-digital converter architecture with selectable transfer characteristic. A delay-matched regeneration detection circuit and the transfer characteristic selection method are also presented. The transfer characteristic selection can be used to improve both resolution and integral nonlinearity of the converter for larger input voltages. A transistor-level implementation, using the United Microelectronics Corporation 130-nm design process, was simulated to confirm the feasibility of the proposed architecture described in this brief.