Multilevel-cell (MLC) memory technologies have achieved a great improvement in increasing demand for a high-density memory. As the memory cells utilize a higher number of bits per cell, they have been faced with some problems, such as accurate charge placement and measurement, which slow down programming processes. To overcome these problems, the new data representation technology, rank modulation coding, is employed for MLC memories. For rank modulation memory, a fast and accurate rank reading among multiple cells is one of the most important functions to be achieved to serve an efficient nonvolatile memory. The existing rank determination methods that compare two currents (memory current and ramp down current) and an array of winner-take-all (WTA) rank determination showed their own limitation in terms of mismatch impacts and area consumption. If the rank determination speed can be improved and the circuits are not affected by the possible impact of mismatch, the rank modulation memory will be a more practical memory as a next-generation memory. This brief presents a new rank read circuitry with much faster rank read time. The read time for 16 cells' ranks is 600 ns, which is much faster than the existing ways. This rank determinator adopted an advanced WTA circuit for the rank read circuitry.