Abstract:
This brief presents a low-power low-distortion high-efficiency class-D audio amplifier. The proposed architecture uses an integral sliding mode controller with a novel on...Show MoreMetadata
Abstract:
This brief presents a low-power low-distortion high-efficiency class-D audio amplifier. The proposed architecture uses an integral sliding mode controller with a novel on-chip continuous current sensor. A full-bridge output stage is used to increase the output power, and an adaptive nonoverlapping-clock generation technique is presented to eliminate the short circuit current. Moreover, the switching frequency is chosen to achieve the highest possible linearity without efficiency degradation. The proposed architecture contains the minimum number of loop amplifiers to reduce quiescent current consumption. The proposed class-D audio amplifier has been implemented using 65-nm CMOS technology and operated from a single 2.7-V voltage supply (using thick oxide transistors) while occupying an active area of 0.31 mm2. Post-layout simulations show that the proposed architecture achieves a total harmonic distortion of 0.002% for a 2.2 Vpp 1-kHz input signal. It achieves a peak efficiency of 96% and a maximum output power of 400 mW at an 8-Ω differential load.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: 63, Issue: 8, August 2016)