This brief introduces a successive approximation time-to-digital converter based on a novel algorithm denoted as successive approximation register with continuous disassembly (SAR-CD). The main advantage of the proposed SAR-CD algorithm is that it moves the conditioning between the evaluated bits to the digital domain, after all the bits are evaluated. Simulation results show promising enhancements in power consumption compared with the state-of-the-art designs. A full 10-bit architecture is introduced using 65-nm CMOS technology as a case study with simulation power consumption of 2.8 mW at a sampling rate of 29.4 Msample/s from 1-V power supply with an effective number of bits value of 8.63 bits and a maximum differential nonlinearity of 1 least significant bit.