This brief presents an efficient architecture of the polar decoder that employs the successive-cancellation (SC) decoding algorithm. In the SC decoding algorithm, each bit is decoded successively by recursively calculating the log likelihood ratio (LLR) based on two kernels. This brief proposes a novel LLR representation scheme so that the kernel processing can be realized in low-complexity and high-speed circuitry. A 1024-bit polar decoder was designed and implemented based on the proposed scheme using a 0.18 μm CMOS process. Its throughput is 252R Mb/s for the rate-R code, and the gate count is 256K. By the proposed LLR representation scheme, the decoding speed is increased by 18% while the gate count is not increased when compared to the same decoder designed with the signed-magnitude scheme. In terms of the throughput efficiency, the proposed decoder is 1.34 times superior to the previous state-of-the-art decoder.